F28069的中断数是96个，分为12组

The PIE block can support 96 individual interrupts that are grouped into blocks of eight.Each
group is fed into one of 12 core interrupt lines (INT1 to INT12)

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比如常用的的CPU0定时器这个中断就是在第一组的第7个，它在代码里面有个名字，TINT0

// Group 1 PIE Peripheral Vectors:PINT     ADCINT1;   // ADC - if Group 10 ADCINT1 is enabled, this must be rsvd1_1PINT     ADCINT2;   // ADC - if Group 10 ADCINT2 is enabled, this must be rsvd1_2PINT     rsvd1_3;PINT     XINT1;	  // External Interrupt 1PINT     XINT2;     // External Interrupt 2PINT     ADCINT9;   // ADC 9PINT     TINT0;     // Timer 0PINT     WAKEINT;   // WD

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F28069在代码里的中断定义


// Define Vector Table:
struct PIE_VECT_TABLE {// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in
// boot ROMPINT     PIE1_RESERVED;PINT     PIE2_RESERVED;PINT     PIE3_RESERVED;PINT     PIE4_RESERVED;PINT     PIE5_RESERVED;PINT     PIE6_RESERVED;PINT     PIE7_RESERVED;PINT     PIE8_RESERVED;PINT     PIE9_RESERVED;PINT     PIE10_RESERVED;PINT     PIE11_RESERVED;PINT     PIE12_RESERVED;PINT     PIE13_RESERVED;// Non-Peripheral Interrupts:PINT     TINT1;     // CPU-Timer1PINT     TINT2;     // CPU-Timer2PINT     DATALOG;   // Datalogging interruptPINT     RTOSINT;   // RTOS interruptPINT     EMUINT;    // Emulation interruptPINT     NMI;       // Non-maskable interruptPINT     ILLEGAL;   // Illegal operation TRAPPINT     USER1;     // User Defined trap 1PINT     USER2;     // User Defined trap 2PINT     USER3;     // User Defined trap 3PINT     USER4;     // User Defined trap 4PINT     USER5;     // User Defined trap 5PINT     USER6;     // User Defined trap 6PINT     USER7;     // User Defined trap 7PINT     USER8;     // User Defined trap 8PINT     USER9;     // User Defined trap 9PINT     USER10;    // User Defined trap 10PINT     USER11;    // User Defined trap 11PINT     USER12;    // User Defined trap 12// Group 1 PIE Peripheral Vectors:PINT     ADCINT1;   // ADC - if Group 10 ADCINT1 is enabled, this must be rsvd1_1PINT     ADCINT2;   // ADC - if Group 10 ADCINT2 is enabled, this must be rsvd1_2PINT     rsvd1_3;PINT     XINT1;	  // External Interrupt 1PINT     XINT2;     // External Interrupt 2PINT     ADCINT9;   // ADC 9PINT     TINT0;     // Timer 0PINT     WAKEINT;   // WD// Group 2 PIE Peripheral Vectors:PINT     EPWM1_TZINT; // EPWM-1PINT     EPWM2_TZINT; // EPWM-2PINT     EPWM3_TZINT; // EPWM-3PINT     EPWM4_TZINT; // EPWM-4PINT     EPWM5_TZINT; // EPWM-5PINT     EPWM6_TZINT; // EPWM-6PINT     EPWM7_TZINT; // EPWM-7PINT     EPWM8_TZINT;	// EPWM-8// Group 3 PIE Peripheral Vectors:PINT     EPWM1_INT;  // EPWM-1PINT     EPWM2_INT;  // EPWM-2PINT     EPWM3_INT;  // EPWM-3PINT     EPWM4_INT;  // EPWM-4PINT     EPWM5_INT;  // EPWM-5PINT     EPWM6_INT;  // EPWM-6PINT     EPWM7_INT;  // EPWM-7PINT     EPWM8_INT;  // EPWM-8// Group 4 PIE Peripheral Vectors:PINT     ECAP1_INT;  // ECAP-1PINT     ECAP2_INT;  // ECAP-2PINT     ECAP3_INT;  // ECAP-3PINT     rsvd4_4;PINT     rsvd4_5;PINT     rsvd4_6;PINT     HRCAP1_INT; // HRCAP-1PINT     HRCAP2_INT; // HRCAP-2// Group 5 PIE Peripheral Vectors:PINT     EQEP1_INT;  // EQEP-1PINT     EQEP2_INT;  // EQEP-2PINT     rsvd5_3;PINT     HRCAP3_INT; // HRCAP-3PINT     HRCAP4_INT; // HRCAP-4PINT     rsvd5_6;PINT     rsvd5_7;PINT     USB0_INT;   // USB-0// Group 6 PIE Peripheral Vectors:PINT     SPIRXINTA; // SPI-APINT     SPITXINTA; // SPI-APINT     SPIRXINTB; // SPI-BPINT     SPITXINTB; // SPI-BPINT     MRINTA;	  // McBSP-APINT     MXINTA;    // McBSP-APINT     rsvd6_7;PINT     rsvd6_8;// Group 7 PIE Peripheral Vectors:PINT     DINTCH1;	// DMA CH1PINT     DINTCH2;	// DMA CH2PINT     DINTCH3;	// DMA CH3PINT     DINTCH4;	// DMA CH4PINT     DINTCH5;	// DMA CH5PINT     DINTCH6;	// DMA CH6PINT     rsvd7_7;PINT     rsvd7_8;// Group 8 PIE Peripheral Vectors:PINT     I2CINT1A;  // I2C-APINT     I2CINT2A;  // I2C-APINT     rsvd8_3;PINT     rsvd8_4;PINT     rsvd8_5;PINT     rsvd8_6;PINT     rsvd8_7;PINT     rsvd8_8;// Group 9 PIE Peripheral Vectors:PINT     SCIRXINTA;  // SCI-APINT     SCITXINTA;  // SCI-APINT     SCIRXINTB;  // SCI-BPINT     SCITXINTB;  // SCI-BPINT     ECAN0INTA;  // eCAN-APINT     ECAN1INTA;  // eCAN-APINT     rsvd9_7;PINT     rsvd9_8;// Group 10 PIE Peripheral Vectors:PINT     rsvd10_1; // Can be ADCINT1, but must make ADCINT1 in Group 1 space "reserved".PINT     rsvd10_2; // Can be ADCINT2, but must make ADCINT2 in Group 1 space "reserved".PINT     ADCINT3;  // ADCPINT     ADCINT4;  // ADCPINT     ADCINT5;  // ADCPINT     ADCINT6;  // ADCPINT     ADCINT7;  // ADCPINT     ADCINT8;  // ADC// Group 11 PIE Peripheral Vectors:PINT     CLA1_INT1;  // CLAPINT     CLA1_INT2;  // CLAPINT     CLA1_INT3;  // CLAPINT     CLA1_INT4;  // CLAPINT     CLA1_INT5;  // CLAPINT     CLA1_INT6;  // CLAPINT     CLA1_INT7;  // CLAPINT     CLA1_INT8;  // CLA// Group 12 PIE Peripheral Vectors:PINT     XINT3;PINT     rsvd12_2;PINT     rsvd12_3;PINT     rsvd12_4;PINT     rsvd12_5;PINT     rsvd12_6;PINT     LVF;        // Latched overflowPINT     LUF;        // Latched underflow
};

CPU 中断使能寄存器IER(interrup enable register)

该寄存器用来配置是否启用中断

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The interrupt flag (IF) bit corresponding to that event is
set in a register for that particular peripheral.
If the corresponding interrupt enable (IE) bit is set, the peripheral generates an interrupt request to the PIE
controller. If the interrupt is not enabled at the peripheral level, then the IF remains set until cleared by
software. If the interrupt is enabled

中断是可以启用和禁止的，者通过IER,IFR两个寄存器来操作，比如一般程序开头，我们会禁用所有中断：

    //// Disable CPU interrupts and clear all CPU interrupt flags//IER = 0x0000;IFR = 0x0000;//清除标志，表示一开始没有任何中断发生

启用中断的话，给IER或上值，比如，启用cup0,1,2，启用了int1,int13,int14这三个组的中断

// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
// which is connected to CPU-Timer 1, and CPU int 14, which is connected
// to CPU-Timer 2:IER |= M_INT1;IER |= M_INT13;IER |= M_INT14;
// Enable TINT0 in the PIE: Group 1 interrupt 7PieCtrlRegs.PIEIER1.bit.INTx7 = 1;