ATSAM4S2A上的PLL无法超过60MHz
在使用ATSAM4S2A芯片的时候，如果需要将PLL频率提升到更高的值，可以按照以下步骤进行操作：
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禁用PLL： // Disable the PLL PMC->CKGR_PLLAR &= ~CKGR_PLLAR_MULA_Msk; while ((PMC->PMC_SR & PMC_SR_LOCKA) != 0);
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配置PLL参数： // Configure PLL parameters uint32_t mul = 10; uint32_t div = 2; uint32_t pll_freq = 120000000UL; uint32_t main_clock_freq = 12000000UL; uint32_t divider = (div == 0) ? 0 : (div - 1);
uint32_t pll_reg_val = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(mul - 1) | CKGR_PLLAR_PLLACOUNT(0x3f) | ((divider << CKGR_PLLAR_DIVA_Pos) & CKGR_PLLAR_DIVA_Msk) | CKGR_PLLAR_PLLAEN;
// Write PLL parameters PMC->CKGR_PLLAR = pll_reg_val;
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等待PLL锁定： // Wait for the PLL to lock while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
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设置PLL为主时钟源： // Select the PLL as the main clock source PMC->PMC_MCKR &= ~PMC_MCKR_CSS_Msk; PMC->PMC_MCKR |= PMC_MCKR_CSS_MAIN_CLK; while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
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配置主时钟分频器： // Configure the main clock prescaler uint32_t prescaler = (pll_freq / main_clock_freq); if (prescaler < 2) { prescaler = 2; }
PMC->PMC_MCKR &= ~PMC_MCKR_PRES_Msk; PMC->PMC_MCKR |= (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_MDIV_EIGHTH_CLK); while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
// Update the